|
Article Excerpt
Original Source: FD (FAIR DISCLOSURE) WIRE
ERIC STRID, CO-FOUNDER, CHAIRMAN, CTO, CASCADE MICROTECH, INC.: Welcome to Cascade Microtech analyst day 2007. Today we have more folks then you normally see. Usually it is Steve and I running around the financial conferences and doing roadshows. And today you will meet John Pence, Willis Damkroger and Jim Rathburn, other key managers running the divisions and closer to the products and customers. This is our rough schedule and feel free to ask questions after each talk. At about 4 o'clock we have some demos set up in the -- across from the parking lot. We will go over and kick some tires and talk some more.
With that, by the way I am Eric Strid, Co-founder and Chief Executive Officer. This talk today will be governed by this Safe Harbor statement. Specifically we're not updating any guidance since the January 24 conference call.
Cascade Microtech provides solutions from chip design and process development through manufacturing tests. We provide engineering probing solutions. This is our S300 Prober. Basically it connects various engineering testers to 300 mm wafers. We are the leader in this space. And the technology, the customer knowledge and cash flows from that business enabled us to create a new technology for production wafer probing. This year we also added test sockets for the -- as another type of production test consumable. And these are used in manufacturing as well. So you'll hear about each of these productlines today.
A summary of our investment profile is that we have a very strong position in engineering probing solutions. And this is a relatively small market, but it generates continuing growth and strong cash flows. In the production consumable space, production probe cards are about $1 billion, and all kinds of test sockets are another $1 billion. So there is very large SAM and TAM opportunities here, and Willis and Jim will talk about those in more detail.
We have shown significant technology differentiation as well as strong growth rates in recent past. We have a very diversified customer base. We have thousands of customers. In any one year we log about 800 customers. We employ lots of patented technologies and trade secrets, and our channels and customer intimacy around the world represent extensive barriers to entry in many of our productlines. And financially we have strong cash flows and improving gross margins.
You have all watched as your cell phone and your laptops and other consumer items increased in power and decreased in size, add more data rates and so forth. This has been enabled by our customers shrinking transistors. As they shrink functions on a chip, they can put more functions on the same size of chip, and this tremendous productivity advancements of Moore's Law.
Where we play it is in electrical metrology. The tools that build the wafers, like the ASML, Applied Materials, Novellus are fabricating the layers. Tools from KLA-Tencor or Rudolph are measuring these devices and structures physically. But to turn on the devices electrically, as they are intended to operate, is our function as electrical metrology for these wafer level products.
Our mission is to be the worldwide market and technology leader in both engineering probing solutions and production test consumables. Production test consumable again is -- covers both, probe cards and chip sockets. What a probe card does is connect a wafer to a tester. And what a socket does is connect a packaged chip to a tester. We're all about connectivity, connectivity in the test domain.
And connectivity it turns out is the problem or the enabler in all kinds of electronics. It turns out at the chip level the interconnects do not scale nearly as well as the transistors, the basic devices on the chips. This ultimately has forced the multicore microprocessor architectures. Because on a chip, it is the interconnects, all the wiring on top that dominates the speed, the power dissipation and the cost of building that chip.
Between chips there is a similar problem that the wiring costs too much and it is too long. That is what has driven stacks of chips, such as memory chips in your cell phone, or the multichip packages in an RF front-end. Between PCs we are all aware that the network bandwidth is the main limitation to performance. And not coincidentally the limitation to a test cell is also connectivity, both the speed of the line, the number of lines, the density of those lines. What we're working on in both the engineering and production divisions are products that provide order of magnitude improvements in productivities and capabilities, for our customers.
This is a simple diagram of we where our products get used in development and in manufacturing. The engineering test labs that we supply are doing process characterization, device modeling, failure and yield analyses, and reliability analyses. This is our typical S300 Prober, very popular for leading-edge development today.
After finished wafers come out of the fab the first test step is parametric step -- parametric tests rather. This is where the fab gets about half of the feedback data for process control. This is just measuring the test transistors between the products on the wafer. This is a little bit like pulling your cookies out of the oven. You poke them to make sure that they're done enough. Have the processes achieved the right process control for making basic elements on the chip?
After parametric tests it goes to various names of wafer probing such as chip sort or class sort, if you are Intel. And this is where most probe cards and probers are used. This is where the products are 100% tested. This is where the fabs get a yield number for how well their product is yielding.
After this test step the product, the wafers, are sewn up and assembled in packages. And after packaging there is a packaged parts test, usually called final test, which use various types of sockets. So you see the analogy of connecting testers to the chips that is packaged with sockets and in a probe card case connecting testers to the chips on the wafer. So there is various test strategies about how each of these are used, but most chips go through most of these steps is a simple way to think about it.
Questions. What percentage of customers are buying all of these things? If you look at major company names, multiple household names, though within those large companies they are totally different groups. The engineering groups don't really even know the production groups often. Smaller companies actually they do and they get more leverage. But usually on a test floor you have to approve your metal regardless of what the engineers say. But there is multiple advantages there. And like when we set up a sales subsidiary in a new country we're serving both the divisions.
One of the reasons we went public is to have the cash and currency to do acquisitions of productlines or technologies or companies. We're not just trying to rollup marginal or average companies. We are going after high-quality opportunities, especially those with nice technology differentiations and margin differentiations and synergies of what we are already doing.
The first of these we announced was in October last year. The eVue digital microscope productline was a joint development with a little company in Boston. They didn't want to ramp up the production. We have ramped it up here now. It is doing very well. There are opportunities for more upgrades within our installed base. And we have already reported significant margin improvements as a result.
In April this year we announced the acquisition of Gryphics Inc. Jim Rathburn was the CEO and Co-founder. I first met Jim about seven years ago, it turns out. And I remember when we saw him, gee, would you like to be acquired, Jim? And eventually that came to pass.
They, we now, are supplying the same high-performance chip customers with sockets as we do with probe cards. So the high-performance digital and the RF applications, we are already addressing with probe cards or sockets, and each one of those product lines open stores for the other. There's a very strong technology and gross margin story here, and I will let Jim talk about more of the details.
This July we also announced we have acquired the assets of our German distributor, extending our space, going direct in another geography. And we have generally found advantageous for revenue margin and service opportunities as we go direct and supply those regions more completely.
We do pay a lot of attention to our intellectual property. We have hundreds of patents in the U.S. and foreign. We do defend those patents. Just last year and earlier this year we won some more settlements, and we have won injunctions over the years. We don't patent everything of course. Here's a number of trade secrets that we keep because it is not verifiable. We have licensed our technologies when appropriate to other fields of use for related companies. And we have also licensed and used other people's technologies. So not invented here is not an issue, we are just being pragmatic about it and trying to get the best competitive advantage.
The management team is well seasoned. We have been through the semiconductor cycles. My Co-founder is still with the Company, a very creative technologist. You won't see Reed today, but you'll see these other Division Managers and Steve, our Chief Financial Officer. Last week we announced that we changed our COO search to a CEO search. And this is part of a planned transition. And I am completely supportive and happy to bring in the next talent that can push us to the next level of growth. I'm looking forward to it. I think it will be very positive for the Company. Next we have John Pence, VP and GM of our Engineering Products Division.
JOHN PENCE, VP, GM ENGINEERING PRODUCTS, CASCADE MICROTECH, INC.: As Eric mentioned, I am John Pence, and I have been with the Company now just a little over 14 years. I'm responsible for what we call the Engineering Products Division. And really what we do is supply critical electrical metrology tools to the very heart of the semiconductor industry. This is really the productivity engine for the entire industry, so you can imagine that a lot of what is happening here is in many ways limited by the ability of these engineering activities to support either the development of new processes, the modeling of devices required to do the critical electrical designs, and then eventually yield enhancement and failure analysis.
And so really our value is providing massive gains in productivity to these engineering activities. You can imagine as consumer product lifecycles have gotten shorter, these engineering activities have now had to become far more productive than they historically have been in order to support that. Otherwise there is no way these companies can get to market in time with the competitive products and make money.
What you see here really is our industry -- the industry standard is our S300 wafer probing tool. These are Cascade manufactured Infinity probes. And these are high frequency probes that are making contact to device bond pads. In this case it is a 90 nanometer transistor that you're looking at. And here you see actually the transistor gates underneath this is the high-k dielectric that you hear so much about in the press. And what you see here are actually the molecules of the gate oxide. These electrical measurement that we enable are being used to help engineers both understand the material science of what they're trying to do, as well as than later on create useful electrical circuits in these semiconductor processes.
And really our industry has had this phenomenal ability to achieve massive gains in productivity over the long run. You see this quoted a lot, but it is absolutely true, and we lived through it. 25 to 30% per year productivity gains is what has actually been achieved in the industry. And this historically has been achieved mostly through smaller devices, so feature shrinks and larger wafers. Now we're sort of reaching a period where wafer size is probably done for a while. Some people are talking about 450 mm, but I don't think it is coming anytime soon. And really the future for productivity gains here is going to come from continued shrinks, so feature size reductions, as well as other kinds of productivity in the equipment and the processes that are being used to develop these new processes.
Shrinks, a very positive market for us for the Engineering Products Division and Cascade in general. Why? Well, smaller devices are leading then to the use of new materials. More complicated interconnect structures, faster speeds in terms of the transistor performance and lower operating voltages are requiring smaller electrical signals to be measured. And so in general that market force is moving toward our strength. The good news is this is in no way limited to 300 mm wafer sizes. Anybody who is in this business, whether it is 200 mm or 150 mm, they're having to do process shrinks in one form or another in order to improve their profitability and their competitive performance in the marketplace.
With respect to interconnect, so smaller devices are also -- so that is a good thing. You're getting higher speeds. You can fit more stuff in the same amount of space. But the problem is in order to route all those electrical connections now becomes pretty complicated. And what you see in this, this is a cross-section of a state-of-the-art chip, and you see a few layers down in here that are required to define the active parts of it, the transistors. But look at all of these layers that are new required basically just to wire it all up. And then because the speeds are faster, the wiring has to actually be better then the historical wiring. And now this is leading to some new complexity in terms of what kind of materials are we going to use in order to not ruin -- you've got these wonderful transistors and then you're going to go ruin the performance by having this crummy wiring trying to connect it altogether. That is not going to work.
This is another critical market for his that, again, we feel is moving in our direction. So we participate not only in the active device and material science end of things, but also in the characterization of these interconnect structures, and also increasingly now in the area of reliability. Because with these smaller geometries now concerned about, hey, I can make the device, but if it isn't reliable, who cares?
And then the third element that, again, we feel is a positive market for us for our business has to do with the increasing complexity in the area of both materials and then even new device types. And so this is -- the main point of this slide is it is very complicated and it will continue to be so. Certainly there are things here you will recognize like low-k dielectrics and high-k dielectrics and wafer level packaging. But in general we're not wedded to any one particular devices concept or interconnect architecture. All of this research activity is good in general for our business, and we provide tools that enable the people doing this work to be more productive.
And with respect to the rising cost of process development you certainly hear a lot of things in the press about how expensive it is as you go from one node to the next. And along with that is the design cost. You're hearing now increasingly people complain that it is really, even if I can make the parts, I'm having difficulty getting accurate models. Or I don't have enough tolerance on my process to get me acceptable circuit yield. And again we participate in all of that.
Really the good news here is because it is so expensive to -- and really what this says is for each change in your process node size, and in this case for a logic process, it costs about 30% more to develop a process. So at 90 nanometers it will cost you about $1 million to create a new semiconductor process. And at 65 nanometers it is going to be $1.3 billion. The stakes are pretty high. It costs a...
|
