Home | Business News | Browse by Publication | P | Printed Circuit Design & Manufacture

SIPs give more to Moore: SiP-based system-level integration resolves CMOS scaling limits.

Article Excerpt
The electronics industry is nearing the limits of traditional CMOS scaling. Although predictions that Moore's Law has reached its limits have been heard for years, they have proved premature. We are now, however, nearing the basic physical limits to CMOS scaling, and the price elastic growth of the industry can no longer continue based solely on Moore's Law scaling. New materials and device architectures in development will eventually provide a path to increased density, increased performance and lower cost beyond the capability of CMOS-based circuits. However, there will be a time lapse between the slowing of traditional CMOS scaling and the rollout of architectures and materials that can support Moore's Law scaling. In the meantime, as scaling become more difficult, packaging innovations are taking up the slack (FIGURE 1).

[FIGURE 1 OMITTED]

The International Technology Roadmap for Semiconductors (ITRS) defines functional diversification, incorporating system-level functions into a single package, as "more than Moore." This approach enables continued rapid progress in functional density during a period where traditional CMOS scaling cannot keep the pace and new architectures are not yet ready. A second key contribution of packaging to maintaining the pace of functional density scaling is 3-D integration. Both these innovations are accomplished through integration of multiple circuit types into a single device using system-on-chip (SoC) and system-in-package (SIP) technologies. As electronics becomes more consumer-dominated, the most important of these will be SiP. ITRS defines SiP as "a combination of multiple active electronic components of different functionality,...

View this article FREE - Now for a Limited Time, try Goliath Business News
Free for 3 Days!