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Size matters: next generation ASIC and FPGA packages with 0.8-mm pitch and over 2,000 pins will require the use of HDI to accomplish BGA routing.

Publication: Printed Circuit Design & Manufacture
Publication Date: 01-FEB-08 		Format: Online
Delivery: Immediate Online Access
Full Article Title: Size matters: next generation ASIC and FPGA packages with 0.8-mm pitch and over 2,000 pins will require the use of HDI to accomplish BGA routing.(BGA BULLETIN)

Article Excerpt
THIS IS THE second in a series of articles on BOA routing methods. My goal is to highlight routing problems associated with large pin-count BOAs, and provide the PCB designer with effective techniques that enable higher route density and reduction of layer count.

The good news is that BGA technology enables high pin-count FPGAs, ASICs and connectors packaged with a very high density array of pins. The bad news is that finer pin-pitches and increased pin-counts are making these devices increasingly difficult to route. The requirement to miniaturize while increasing functionality is the most significant constant driving change in our industry. Fortunately, it keeps skilled PCB designers (and former designers like me working for software vendors) employed!

High Pin Counts

The current crop of BOAs with less than a 1-mm pitch are not yet pushing high pin-count and as such they...

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