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PCI Express: connectivity for the next generation.

Article Excerpt
Since its inception in 1992, the PCI bus has become the I/O backbone of nearly every computing platform, and is the primary interface for desktop computers and peripheral cards. PCI technology has played a large part in the standardization of computer hardware, and has provided an evolving platform for increasing performance demands.

The PCI bus was designed for high-speed, efficient data movement using the local bus architecture--directly interfacing with the computer's central processing unit (CPU). Performance of the PCI bus has been continually improved to keep pace with increased bandwidth requirements by increasing clock speeds and widening buses. However, those methods have begun to run up against some boundaries. Increasing bus speed is no longer practical, due to the effects of increased signal skew. Widening the bus complicates board and silicon layout. Close examination of PCI signaling technology reveals that the parallel bus architecture of PCI is reaching its performance limits.

To combat these performance limitations, the PCI Express architecture was recently introduced to provide a scalable, high-speed, serial I/O bus. While the new bus maintains backward compatibility with existing PCI applications and drivers, lessening the burden on developers, the form factor of the new PCI Express slots differs from the current PCI slots, meaning any end user wishing to utilize a PCI Express card must have...

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