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Simulate, emulate, or hope for the best?

Publication: Test & Measurement World
Publication Date: 01-APR-09 		Format: Online
Delivery: Immediate Online Access

Article Excerpt
Ron Wilson, Executive Editor, EDN

Once upon a time, you verified a logic design for an FPGA (field-programmable gate array) by compiling it, loading it, and pushing the reset button on your evaluation board. But as FPGAs have become larger, this "Blow-and-Go" verification style, as Xilinx director of software product marketing Hitesh Patel...

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