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Diagnosis-driven yield analysis.

Publication: Test & Measurement World
Publication Date: 01-DEC-08
Format: Online
Delivery: Immediate Online Access

Article Excerpt
By Dave Macemon, Mentor Graphics

Shorten the path to finding the root cause of yield-limiting systematic defects for advanced IC designs.

Numerous challenges have to be overcome during design and production of ICs below 90 nm. Manufacturing processes are still being characterized, and the interactions between the physical processes and design features can be extremely subtle and difficult to identify. As a result, meeting yield goals is a bigger challenge than it was at larger technology nodes, and this has a direct impact on profits. The faster a new design can be ramped up to volume production rates, the faster the time to profit (Figure 1).

Yield management has traditionally been the responsibility of one or more engineers who also are responsible for design, test, production, or processing. Once a design is in production, the yield manager's job is to make the product "yield better" by, among other things, identifying yield limiters and specifying changes to the design, test, or manufacturing process. Finding the root cause of yield-limiting defects often requires engineers to sort through a large amount of information from many different sources, a process that can take months.

A yield manager usually depends on manufacturing process data such as parametric measurements and in-line inspection data when making an analysis. From the performance history of the manufacturing equipment, the yield manager can see which machines have recurring maintenance issues. Electrical scribe-line tests also can provide an early indication that process variations are starting to drift more than expected.

During wafer sort, test sets or patterns generated using ATPG (automatic test pattern generation) software are applied to the die on ATE (automated test equipment). At this point, the yield manager often uses a spreadsheet to plot the cumulative errors from many wafers into a single wafer map that helps identify a failure "signature."

The yield manager then selects a set of die that most likely contain the yield-limiting defect and...

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